The present invention relates generally to electronic circuits used to generate clock signals and in particular to digital phase-locked loops (PLLs) and fractional-N PLLs.
A phase-locked loop (PLL) is a system that generates an output signal whose phase is in lock with that of a reference signal. Because phase is the integral of frequency over time, the frequency relationship between the input and output signals is guaranteed when the PLL is locked. The output signal is obtained from an oscillator whose frequency can be controlled, usually by a voltage or current in analog systems, or by a digital code in digital systems. By comparing the phases of the output signal and the reference signal, a control parameter is obtained. The control parameter can adjust the oscillator frequency upward if it is too low compared to the reference frequency, or downward if it is too high. It is typically filtered by a low-pass filter to prevent that the oscillator changes too quickly.
The output frequency of a PLL may be a multiple of the reference frequency. To achieve this, a divider is inserted in the feedback loop. For instance, a divide-by-two block achieves that the output frequency equals twice the reference frequency. In general, dividing by N achieves that the output frequency equals N times the reference frequency. Dividers may be fixed, but are usually programmable. It is very easy to build a digital circuit that divides a frequency by an integer number, hence the most common class of PLLs is called integer-N. A disadvantage of integer-N PLLs is that the frequency resolution is low. The minimum distance between two frequencies that can be programmed equals the reference frequency. Using a reference frequency that is too low results in unacceptable jitter.
It is also possible, but more complicated, to divide by a non-integer number. The class of PLLs with this capability is called fractional-N PLLs. Non-integer division is often achieved with an integer divider, by programming it at the nearest higher integer for part of the time, and at the nearest lower integer for another part of the time. The partitioning of the time determines the average fraction. While yanking up or down the resulting control parameter can cause jitter of the oscillator, this can be reduced by the loop filter. However, the loop filter also limits the ability of a PLL to respond fast, e.g. the time to first lock to a reference frequency or the timely ability to follow changes in the reference frequency, and for some applications response time and jitter requirements can not be met by this approach.
Another PLL architecture uses a time-to-digital converter (TDC) in the feedback loop. A TDC can count the number of pulses of the output signal during a cycle of the reference signal. Again, achieving integer precision is easy. A TDC can be designed with fractional precision, too, enabling a very low-jitter fractional-N PLL. This approach usually requires a mixed-signal design TDC (partially digital, partially analog). To obtain a high fractional resolution, a TDC may require a lot of parallel fast analog circuitry, and therefore the PLL may dissipate relatively much power. This can create problems in many systems, especially those that are battery-powered.
In some applications, the output clock signal of the PLL must complete the correct number of cycles during a period when lock is lost. Over the time when the PLL is out of lock, the phase error may exceed the period of the reference clock signal. A conventional PLL is unable to track phase errors greater than one reference clock cycle without special additional circuitry, so it will not guarantee that the correct number of cycles have occurred if the phase error exceeds this range.
Some applications use multiple reference signals. This may for instance be the case when the best reference signal is not always available, but there are some backup reference signals that can be used instead. Or the system may have multiple modes, where each mode provides its own reference signal. When a PLL switches reference signals, even those that have the same frequency, it may be temporarily out of lock because the prior and the new reference signal may not have the same phase. To achieve hitless switching, some PLLs may temporarily “loosen” the loop filter to achieve faster lock—at the expense of high jitter—or “tighten up” the loop filter to smooth the transition—at the expense of locking even later.
There is an unmet need to simultaneously achieve high frequency resolution, low jitter, fast response time, tracking arbitrary large phase errors, and low power. There is also an unmet need to achieve hitless switching without losing lock. Embodiments of the present invention address these needs.